1. Field of the Invention
Example embodiments of the present invention relate generally to a non-volatile memory device and method thereof.
2. Description of the Related Art
Storage devices, such as volatile memories and non-volatile memories, may be included within conventional mobile devices, such as MP3 players, portable media players (PMPs), mobile phones, notebook computers, personal digital assistances (PDAs), etc. Conventional mobile devices may include relatively high storage capacities so as to provide higher functionality (e.g., video recording, pictures, etc.). A conventional multi-bit memory device storing 2-bit data or multi-bit data in a single memory cell may allow memory cells to obtain a higher storage density.
If 1-bit data is stored in a single memory cell, the memory cell may have a threshold voltage belonging to one of two threshold voltage distributions. That is, the 1-bit memory cell may have two threshold voltage ranges, distributions or “states” corresponding to a first logic level (e.g., a higher logic level or logic “1”) or a second logic level (e.g., a lower logic level or logic “0”). In another example, if 2-bit data is stored in a single memory cell, the memory cell may include four separate voltage distributions corresponding to four respective states (e.g., “00”, “01”, “10”, “11”).
FIG. 1 illustrates logic states of a conventional 2-bit memory cell. Referring to FIG. 1, the threshold voltage distributions may be controlled in order for the threshold voltage distributions corresponding to the four states be determined within set threshold voltage windows, respectively. An incremental step pulse programming (ISPP) process may be used to control the threshold voltage distributions.
In a conventional ISPP scheme, a threshold voltage may be adjusted by fixed increments of a program voltage during an iterative program loop. Thus, setting a relatively low fixed increment for the program voltage may allow the threshold voltage distributions to be controlled more precisely, such that sufficient margins between different threshold voltage distributions may be maintained. However, if the fixed increments of the program voltage are lower, more time may be required to execute the ISPP process. Thus, the increment of the program voltage may be determined based on a tradeoff between threshold voltage distribution control and execution time.
Even if the ISPP scheme is used, a threshold voltage distribution of each state may become wider, which may likewise reduce the margins between neighboring voltage distributions and increase a likelihood of a memory error (e.g., during a read operation), than a desired window due to any of a number of factors.
FIG. 2 illustrates electric-field coupling/F-poly coupling occurring between conventional memory cells.
Referring to FIG. 2, the threshold voltage distribution may increase because of coupling between adjacent memory cells. The coupling may be referred to as “electric field coupling” or “F-poly coupling”. For example, in FIG. 2, it may be assumed that a memory cell MCA may be cell programmed to have any one of four states, and a memory cell MCB may be a cell that programmed to have any one of four states. Under such assumptions, as the memory cell MCB is programmed, charges may accumulate in a floating gate FG. Then, a potential of a floating gate FG of the adjacent memory cell MCA may increase due to coupling with the floating gate FG of the memory cell MCB. A threshold voltage increasing in this manner may be maintained because of the coupling between the floating gates even after the programming operation. The memory cell MCB may include memory cells placed in a word line direction and/or a bit line direction with respect to the memory cell MCA. The coupling between the floating gates of the respective memory cells may cause a threshold voltage of the programmed memory cell MCA to increase, and the threshold voltage distribution may likewise increase, as indicated by the dotted lines of FIG. 2.
A conventional flash memory device may include cells (hereinafter, referred to as a “flag cell”) for storing information (hereinafter, referred to as “flag information”) related to rows (or pages). The flag information may be programmed into the flag cell under the same conditions as those of main cells belonging to the same row/page.
FIG. 3 is illustrates a program process for conventional flag cells. Referring to FIG. 3, in an example, it may be assumed that each row includes two pages. If a memory cell {circle around (1)} (e.g., placed at an intersection between BLe and WL0) of an even-numbered page belonging to a given row (e.g., WL0) is programmed, a corresponding flag cell {circle around (1)} (e.g., placed at an intersection of FBLe and WL0) in a flag cell region may be selectively programmed. Also, if a memory cell {circle around (2)} (e.g., placed at an intersection of BLo and WL0) of an odd-numbered page belonging to a given row (e.g., WL0) is programmed, a corresponding flag cell {circle around (2)} (e.g., placed at an intersection of FBLo and WL0) in the flag cell region may be selectively programmed. Likewise, if a memory cell {circle around (3)} (e.g., placed at an intersection of BLe and WL1) of an even-numbered page belonging to the next row (e.g., WL1) is programmed, a corresponding flag cell {circle around (3)} (e.g., placed at an intersection of FBLe and WL1) in the flag cell region may be selectively programmed. Further, if a memory cell {circle around (4)} (e.g., placed at an intersection of BLo and WL1) of an odd-numbered page belonging to the row (e.g., WL1) is programmed, a corresponding flag cell {circle around (4)} (placed at an intersection of FBLo and WL1) in the flag cell region may be selectively programmed.
Referring to FIG. 3, an arrow may indicate F-poly coupling that a previously-programmed cell may receive if a given cell is being programmed. For example, if the flag cell {circle around (2)} is programmed, the flag cell {circle around (1)} may receive F-poly coupling due to the flag cell {circle around (2)}.
In a conventional multi-bit flash memory device, flag cells may be configured to have a threshold voltage associated with the uppermost or highest threshold voltage distribution. Because flag cells may be programmed to have a threshold voltage associated with the uppermost threshold voltage distribution, a threshold voltage of a previously-programmed cell may increase due to the F-poly coupling if an adjacent cell is programmed. For example, referring to FIG. 3, the flag cell {circle around (1)} may receive the F-poly coupling during a program operation of each of the flag cells {circle around (2)}, {circle around (3)}, and {circle around (4)}, which may cause the threshold voltage of the flag cell {circle around (1)} to increase. Similarly, the flag cells {circle around (2)} and {circle around (3)} may also receive the F-poly coupling, and the threshold voltages of the flag cells {circle around (2)} and {circle around (3)} may also increase. The increase in the threshold voltage of the flag cell may decrease an on-cell current flowing through a string of the flag cells during a read operation, which may increase an occurrence of read errors.